Hello, nice to virtually meet you! I’m Peter S Magnusson; entrepreneur, software guy, blogger (sort of), proud Dad of Two, tech executive. Thank you for stopping by!
My current day job is VP of Engineering at Snapchat, in Venice Beach. You might have heard of us. We’re the leader in a new communication medium, one that leverages the new digital reality – Internet everywhere, fast+easy media creation, and ephemerality. Or as our CEO and Co-Founder recently put it:
Talking through content not around it. With friends, not strangers. Identity tied to now, today. Room for growth, emotional risk, expression, mistakes, room for YOU.
I am having a blast at Snapchat. We’re located in Venice, CA (!); the team is incredible; the opportunity slightly dizzying. And by the way, we are hiring.
Before Snapchat I was Engineering Director at Google, in the Google Cloud Platform business area, where I ran Google App Engine (GAE) for over three years. GAE is arguably the first, largest, and most influential Platform as a Service (“PaaS”) approach to cloud computing. I wrote a bit about the new approach to computing on this blog back in 2009. That blog posting was what prompted me to want to work with cloud computing at Google. Cloud in general is in it’s infancy, and the future is in higher levels of abstraction – developers want to write applications, not wear pagers. While at Google, I met the Snapchat team; they’re famously large customers of GAE.
Before Google I had a brief interlude at Conformiq, where I worked, of all things, as VP of Marketing. Conformiq’s products are in model based testing (MBT). It’s a great developer technology, used much too little in software engineering, if you ask me.
Before that I was dabbling in Yet Another Internet Company. The world clearly needed that. With some friends I worked on “SQ2” – Square Two Technology. We never launched, but the overall problem I was looking to solve (and still want to get around to solving) is the challenge of Quality on the Web. We tried revisiting the problem with the new generation of Internet technologies. Hence the name of the company. (Get it? Second attempt at the public square?)
Prior to SQ2, I worked for a company in a somewhat different space – what would today be labeled virtualization. I founded Virtutech in 1998 as a spin-out from the Swedish Institute of Computer Science, where I had a wonderful time as a computer scientist for a number of years. Virtutech commercialized the Simics simulation platform based on our research in full system simulation: the notion of completely modeling a future electronic system (computer, flight controller, set-top box, router, PDA, etc) prior to hardware. Simics has had some significant academic and commercial success, see the Bibliography below. I was very proud to be elected AMC Fellow in 2011 based on this work. Commercially it went reasonably well too, we sold to Intel in 2010; Intel recently (December 2013) dedicated a full issue of Intel Technology Journal, which was very nice of them (“Simics technology has been used to help develop complex software and hardware systems for more than two decades” – I’m getting old).
I started this blog in April 2007, while attending the 2007 Web 2.0 conference in beautiful San Francisco. Many years ago I was a columnist for Datateknik, at the time Sweden’s premier computer trade rag. That was back in the day when stuff was printed. One of the reasons I stopped writing columns was because of the way printed media works. If I were critical of something, I would get slammed by the PR people of the company that was affected, across various media where they had sympathetic journalists. And I had no effective means of responding, especially if my response needed to be long-winded, with references etc, which of course on technical topics frequently was the case. So slamming Apple for asserting that PowerPC would beat out x86 on performance got me in trouble, as did slamming Ericsson for promoting WAP as the future for Internet on cell phones. (You win a cigar if you can figure who ended up being right.)
In the world of blogs, that’s all changed. I can update any blog entry, or add comments, or respond to comments, or quickly add new related blog entries. Or, if I’m actually wrong about something (imagine that!), I can retract and/or clarify.
The blog as a vehicle for opinion pieces is simply a significant step forward. Of course, not all of the daily 100,000 new blogs have significant things to say, but every now and then one of them does, and the magic of crowd sourcing has a good chance of highlighting it.
Notably, at the same time, the Internet has pretty much crushed the business models for such opinion pieces. This leaves the world in a bit of a limbo: the technology is there to easily communicate, but because the business models have been unbundled (look it up), less is being done instead of more. Hopefully that will change. I’m not dead yet, and I hope to get around to contributing to some sort of solution, one day.
Below is a reasonably complete bibliography, up through 2007. Haven’t really “published” much since then. I haven’t included press coverage of anything I’ve done at Conformiq, Google, or Snapchat. Basically, I put this here so I had some location to point to for whatever street cred in academics I may have claim to.
Most of my published (peer reviewed) work has been in the area of full system simulation, which today would be viewed as a flavor of virtualization. Most press coverage is of my role as Founder and CEO of Virtutech, whose flagship product Simics models high-end electronic systems to support software development and testing. A number of years ago I also wrote a regular column in Datateknik, which at the time was Sweden’s premier computer magazine for professionals, and I’ve included those, as well as including various keynotes and presentations.
Simics has also been extensively used in academia as a research platform for computer architecture and, to a lesser degree, operating systems. At the end I’ve added a “Simics Bibliography” that covers a selection of that research.
Virtualized Software Development: Better Than The Real Thing, Electronic Design, February 20, 2007
Industry Scan: Software Platform, Avionics Magazine, February 1, 2007
Virtutech counting on Aerospace Companies, Aviation Week, January 1, 2007
Debugging Multicore Processors with Virtualized Software Development, ECN Magazine, January 3, 2007
What new technologies will help embedded development? Jack makes a stab at some predictions, Embedded.com, January 1, 2007
Modernizing the development process with virtualized software development: Virtual development platforms well-suited to take on multicore challenges, Military Embedded Systems, September 29, 2006
Simulation May Be Key for Multicore Debugging, FTPOnline, September 18, 2006
Full-System Simulation, SOC Central, September 11, 2006
Case Study: SwitchCore’s deployment of Simics from Virtutech, Chip Design Magazine, Aug 28, 2006
A Simulation-Based Approach to Debugging, Electronics News, July 19, 2006
My predictions: Embedded trends in the next 12 months [PDF], PC/104 and Small Form Factors Resource Guide, July 2006
Software Executive Calls for ‘Nightly Builds’, Design News, June 26, 2006
Commercial Virtuality, Embedded Technology Journal, June 13, 2006
Iridium: Developing Satellite Software Using Simics , Embedded Star, May 23, 2006
Virtutech Technology To Create Virtual Model Of Switch Chip , EE Times, May 15, 2006
Models Solve the Hardware/Software Challenge, ElectronicsWeekly, May 12, 2006
Embedded Systems Survey Reveal Debugging is Top Problem, EDA Geek, May 3, 2006
Debugging is No. 1 challenge, survey finds, EE Times, May 3, 2006
Embedded development with pre-silicon access to chips, Application Development Trends, April 24, 2006
The Need for Concurrent Hardware/Software Design in the Age of Multicore, SOC Central, April 24, 2006
ESC Round One: Cool and Groovy Galore, Embedded Technology Journal, April 4, 2006
Virtutech claims first simulation model of Freescale MPC8641D, EE Times, April 4, 2006
Innovative Engineering: Using Full-System Simulation for Semiconductor System Design, FSA Forum, March 2006
Multiprocessor Debugging, EE Times, March 27, 2006
Biting Bugs Back, “System Level Simulation Speeds Software Debugging”, Embedded Technology Journal, March 14, 2006
Iridium Tests Satellite Software on the Ground (subscription), “Engineers at Iridium Satellite LLC have hired the services of a Silicon Valley simulation firm to help them deal with the problems of controlling and upgrading the company’s 77 low Earth orbit communications satellites, all of them slightly different.”, Aviation Week, March 6, 2006
Simulating and debugging multicore behavior , Embedded.com, February 28, 2006
Podcast: Debugging and Full System Simulation, Peter S. Magnusson explains how multiprocessing is driving the need for simulation in systems-level debugging. (MP3, 4:37 mins.), Dr. Dobbs Podcasts, February 2, 2006
Podcast by Virtutech CEO John Lambert, CafeNews, May 19, 2005
Device Simulation Benefits From Hindsight , Software Development Times, November 1, 2005
Iridium Simulates Space Software with Simics, Application Development Trends Magazine, October 31, 2005
New CEO John Lambert on Virtutech Present and Future, Virtual Strategy Magazine, October 2005
Virtutech system-level simulator features Hindsight technology, EE Times, October 3, 2005:
The Virtues of Virtualization, CIO, September 15, 2005
Debugging Survey Says: What Works, What Doesn’t, Electronic Design, July 21, 2005
Software bug zappers get a virtual helper (requires registration), The Mercury News, June 27, 2005
Développement et test de logiciels de systèmes électroniques complexes , CIE Online, June 2005
Simics Hindsight: Reverse Execution for Software Debugging , Virtual Strategy Magazine, May 4, 2005
System Simulator Runs Program Backward , Electronic Design, April 28, 2005
Simulation App Performs Reverse Debugging , EE Product News, April, 2005
An ESC Buzz Around Real-Time Java, Linux , SD Times, April 1, 2005
Cool EDA products light up 2005 , eeTimes, March 14, 2005
In Hindsight, SW debug can run backward, eeTimes, March 7, 2005
Peter S. Magnusson, “Från Kista till Kiseldalen” (from Kista to Silicon Valley), invited talk, 20th Anniversary Presentation, SICS, May 12th, 2005
‘Invisible’ Computing , PhysOrg.com, December 7, 2004
Simulationsföretag tar in nya pengar från USA , Svenska Dagbladet, December 6, 2004 (in Swedish)
Svenska Virtutech allt mer amerikanskt , Ny Teknik, November 30, 2004 (in Swedish)
Full System Virtualization: Simulation for the Real-Time Embedded Economy , RTC Magazine, November 1, 2004
Full System Simulation: Software Development’s Missing Link , Computerworld, October 20, 2004
Virtutech: Large System Virtualization for Complex Modeling , Virtual Strategy Magazine, October 13, 2004
Ericsson vill koppla upp alla apparater, Elektroniktidningen, October 12, 2004 (in Swedish)
Simulation généralisée de systèmes : Echappez-vous du monde réel , EETimes.fr, October 11, 2004 (in French)
Les systèmes complets ont leur simulation logiciel , Electronique, October 8, 2004 (in French)
The virtual test rack exceeds reality , EE Times, October 4, 2004
Full System Simulation: Escape From Reality , Electronic Design, September 20, 2004
Simulator boggles the mind, EEdesign, August 26, 2004
Ericsson styr svenskpräglat EU-projekt, Elektroniktidningen, August 26, 2004 (in Swedish)
Less is More for DAC 2004, SemiView, July 6, 2004
Simulation Platform Delivers Significant Time Savings,, EE Product News, June 2004
Full System Simulator Creates Virtual Test Labs,, Electronic Design, May 24, 2004
Software creates virtual test laboratory,, Embedded.com, May 20, 2004
It’s Show Time,, Embedded Systems Programming, May 6, 2004
Virtutech’s Simics simulates, tests, complex distributed environments,, iApplianceWeb, May 3, 2004
People on the Move – Virtutech,, San Jose Mercury New, April 10, 2004 (free registration required)
Virtutech Receives $5 Million,, Wall Street Journal, April 4, 2004 (subscription required)
Simulera system snabbt som prototyp,, Elektronik i Norden, March 5, 2004 (in Swedish)
Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson: Performance Simulation Tools. IEEE Computer 35(2): 38-39 (2002)
Is Simulation as Good as The Real Thing?,, eWeek, April 22, 2002
Full system simulation platform offers framework for hardware and software design, Portable Design, February 11, 2002 (requries free registration)
Peter S. Magnusson, “Some Thoughts on Simulation”, invited keynote, 16th Annual Parallel and Distributed Simulation Symposium (PADS), May 13th, 2002
Simulated to get Golden Mouse, Competence, November 22, 2001 (in Swedish)
Presentation of the winners of the Golden Mouse award, Dagens IT, October 22, 2001 (in Swedish)
Candidates for “Guldmusen” prize revealed, Datateknik 3.0, September 13, 2001 (in Swedish)
AMD offers Linux simulator for 64-bit chips, CNET News.com , January 31, 2001
Swedish technology helps AMD, Datateknik 3.0, January 25, 2001 (in Swedish)
Processor giant buys help from Sweden, Ny Teknik, January 24, 2001 (in Swedish)
AMD uses Swedish simulator, Computer Sweden, January 22, 2001 (in Swedish)
AMD chooses Swedish development tool, Elektroniktidningen, January 17, 2001 (in Swedish)
Swedes help AMD compete with Intel, Dagens IT, January 17, 2001 (in Swedish)
AMD signs Swedes to build better SledgeHammer sim, The Register, January 16, 2001
AMD offers developer tools for 64-bit chips, News.com, January 16, 2001
AMD To Use Virtutech To Simulate Hammer Chip, Techweb, January 16, 2001
Switchcore’s founder invests in Virtutech, Dagens IT, December 8, 2001 (in Swedish)
Magnusson, P.; 2000:10 – “Hitta Framtidsföretaget”, column in Dateteknik
Magnusson, P.; 2000:06 – “Bill behöver bada – i stål”, column in Dateteknik
Magnusson, P.; 2000:04 – “Intelligenta datorer i min livstid”, column in Dateteknik
Lars Albertsson, Peter S. Magnusson: Using Complete System Simulation for Temporal Debugging of General Purpose Operating Systems and Workload. MASCOTS 2000: 191-198
Imaginary world – a must for real analysis, Datateknik 3.0, October 12, 2000 (in Swedish)
The companies competing for this year’s Golden Mouse, Datateknik 3.0, September 9, 2000 (in Swedish)
Swedish Virtutech simulates the Internet, http://news.idg.se/, September 1, 2000. (in Swedish)
Swedish testing tool simulates the Internet, http://news.idg.se/, August 24, 2000. (in Swedish)
Simulates computer network, Datateknik 3.0, No. 12, August 24, 2000. (in Swedish)
Swedish product simulates the Internet, Computer Sweden, August 1, 2000. (in Swedish)
Special: Sweden’s 500 Largest IT companies – People of the Future , Veckans Affärer, May 29, 2000. (No longer available on the Web)
Swedish technology tests the computers of the future, Dagens IT, May 18, 2000. (in Swedish)
Swedish company spearheads computer technology simulation , Computer Sweden, May 12, 2000. (in Swedish)
Transmeta’s Crusoe processor uses Swedish technology; Crusoe on notebook computers threatens Intel, Datateknik 3.0, no. 7, 2000. (in Swedish)
Winners of Ny Teknik’s design contest,, Ny Teknik, no. 15, 2000. (in Swedish)
Magnusson, P.; 1999:05 – “WAP är en dödsryckning”, column in Dateteknik
Virtutech advances in the US (No longer available on the Web), Datateknik 3.0, no. 6, 1999.
Researchers at Chalmers decide future of AXE (No longer available on the Web), Elektroniktidningen, Number 8, 1999. (in Swedish)
Virtutech Commercializes Simics, Ercim News, Number 37, April 1999.
Magnusson, P.; 1998:20 – “Microsofts glansdagar är förbi”, column in Dateteknik
Magnusson, P.; 1998:16 – “Befria Windows”, column in Dateteknik
Magnusson, P.; 1998:12 – “Är Intel hotat?”, column in Dateteknik
Magnusson, P.; 1998:09 – “Musen som röt”, column in Dateteknik
Magnusson, P.; 1998:07 – “Varför Linux erövrar världen, column in Dateteknik
Magnusson, P. S, Fredrik Dahlgren, Håkan Grahn, Magnus Karlsson, Fredrik Larsson, Fredrik Lundholm, Andreas Moestedt, Jim Nilsson, Per Stenström, Bengt Werner. 1998. SimICS/sun4m: A Virtual Workstation. In Proceedings of the 1998 USENIX Annual Technical Conference (USENIX’98). June 15-19.
Peter simulates entire computer architectures , Elektroniktidningen, Number 18, 1998. (No longer available on the Web)
Create tomorrow’s processors today, Datateknik, Number 15, October 1998. (in Swedish), (In the special issue on new rising Swedish IT companies.)
Magnusson, P.; 1997:18 – “Följde du också börsraset live på Internet?”, column in Dateteknik
Magnusson, P.; 1997:16 – “Det finns fler poliser på nätet än i Pressbyrån”, column in Dateteknik
Magnusson, P.; 1997:14 – “Har gratisprogrammen en framtid?”, column in Dateteknik
Magnusson, P.; 1997:12 – “Svenskar, kreditkort och Orientexpressen”, column in Dateteknik
Magnusson, P.; 1997:10 – “Ta hand om händerna”, column in Dateteknik
Magnusson, P.; 1997:08 – “Gör långfilm i källaren”, column in Dateteknik
Magnusson, P.; 1997:06 – “50 år fram och tillbaka”, column in Dateteknik
Magnusson, P.; 1997:04 – “AI? När datorer är dummare än pissoarer?”, column in Dateteknik
Magnusson, P.; 1997:02 – “1997: Webbens år — och lite Digital”, column in Dateteknik
Magnusson, P.S. 1997. Efficient instruction cache simulation and execution profiling with a threaded-code interpreter. In Proceedings of the Winter Simulation Conference (WSC’97). December 7-9.
Magnusson, P. S. and J. Montelius. 1997. Performance debugging and tuning using an instruction-set simu¬la¬tor. SICS Technical Report T97:02.
Johan Montelius, Peter S. Magnusson: Using SimICS to Evaluate the Penny System. ILPS 1997: 133-147
Bengt Werner, Peter S. Magnusson: A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems. MASCOTS 1997: 73-80
Magnusson, Peter and Johan Montelius. SICS Technical Report T97:02. Performance Debugging and Tuning using an Instruction-Set Simulator. June 1997.
Larsson, Fredrik, Peter Magnusson, Bengt Werner. SICS Research Report R97:03. SimGen: Development of Efficient Instruction Set Simulators. November, 1997
Magnusson, P.; 1996:21 – “Fackkunskap är viktigt!”, column in Dateteknik
Magnusson, P.; 1996:17 – “Digitala dollar förblir en dröm”, column in Dateteknik
Magnusson, P.; 1996:15 – “Web PC naturlig utveckling”, column in Dateteknik
Magnusson, P.; 1996:13 – “Java ett lyft – för Windows”, column in Dateteknik
Magnusson, P.; 1996:11 – “En mjukvarusaga i sju kapitel”, column in Dateteknik
Magnusson, P.; 1996:08 – “Apple’s Våndor”, column in Dateteknik
Magnusson, P.; 1996:05 – “Kartkriget: Gates vs Negroponte”, column in Dateteknik
Magnusson, P.; 1995:20 – “100 gånger snabbare programmerare har ingen plats i Sverige”, column in Dateteknik
Magnusson, P.; 1995:18 – “Rör inte min e-post!”, column in Dateteknik
Magnusson, P.; 1995:16 – “En kopp Java och Netscape 2.0, tack!”, column in Dateteknik
Magnusson, P.; 1995:14 – “Programera på nätet”, column in Dateteknik
Magnusson, P.; 1995:12 – “Mer porr i kiosken än på Internet”, column in Dateteknik
Magnusson, P.; 1995:10 – “Så erövrade Bill världen”, column in Dateteknik
Magnusson, P.; 1995:08 – “Jag är en kryptoanarkist”, column in Dateteknik
Magnusson, P.; 1995:06 – “VLIW är Intels vapen mot Risc-utmaningen”, column in Dateteknik
Magnusson, P.; 1995:04 – “Lär av den störste programmeraren”, column in Dateteknik
Magnusson, P. S. and B. Werner. 1995. Efficient mem¬ory simulation in SimICS. In Proceedings of the 28th Annual Simulation Symposium, 62-73.
Peter S. Magnusson, Bengt Werner: Efficient memory simulation in SimICS. Annual Simulation Symposium 1995: 62-73
Seif Haridi, Khayri A. M. Ali, Peter Magnusson: Euro-Par ’95 Parallel Processing, First International Euro-Par Conference, Stockholm, Sweden, August 29-31, 1995, Proceedings Springer 1995
Magnusson, P.; 1994:8 – “Emulering är förlorarnas teknik”, column in Dateteknik
Magnusson, P.; 1994:6 – “Apples naiva förhoppningar”, column in Dateteknik
Magnusson, P.; 1994:18 – “Patent på program chans för svenskar”, column in Dateteknik
Magnusson, P.; 1994:16 – “Det papperslösa kontoret är inne”, column in Dateteknik
Magnusson, P.; 1994:14 – “En personlig digital hjälpreda”, column in Dateteknik
Magnusson, P.; 1994:12 – “Chans till storslam med Windows’95”, column in Dateteknik
Magnusson, P.; 1994:10 – “Parallel PC snart på var mans bord”, column in Dateteknik
Magnusson, P. S. and D. Samuelsson. 1994. A compact intermediate format for SIMICS. Technical Report T94:17, Swedish Institute of Computer Science.
Peter S. Magnusson, Anders Landin, Erik Hagersten: Queue Locks on Cache Coherent Multiprocessors. IPPS 1994: 165-171
Magnusson, Peter, Anders Landin and Eric Hagersten. SICS Research Report R94:07. Efficient Software Synchronization on Large Cache Coherent Multiprocessors. Mars 1994
Magnusson, Peter and Bengt Werner. SICS Research Report R94:16. Some Efficient Techniques for Simulating Memory. September 1994
Magnusson, Peter and David Samuelsson. SICS Research Report R94:17. A Compact Intermediate Format for SIMICS. September 1994.
Magnusson, P.; 1993:03 – “2040 får människan ett nytt medium, datorgrafik, column in Dateteknik
Magnusson, P. S. 1993a. A design for efficient simulation of a multiprocessor. In Proceedings of MASCOTS, 69-78.
Magnusson, P. S. 1993b. Partial Translation. Technical Report T93:05, Swedish Institute of Computer Science.
Magnusson, Peter. SICS Technical Report T93:05. Partial Translation. October 1993.
Magnusson, P. S. 1992. Efficient simulation of parallel hardware. Masters thesis. Royal Institute of Technology (KTH), Stockholm, Sweden.
Jim Nilsson, Fredrik Dahlgren, Magnus Karlsson, Peter S. Magnusson , and Per Stenström, Computer System Evaluation with Commercial Workloads, in Proceedings of the 1998 IASTED Conference on Modelling and Simulation, pp. 293-297, May 1998., 1998
Peter S. Magnusson, Fredrik Dahlgren, Håkan Grahn, Magnus Karlsson, Fredrik Larsson, Fredrik Lundholm, Andreas Moestedt, Jim Nilsson, Per Stenström, and Bengt Werner, SimICS/sun4m: A Virtual Workstation, in Usenix Annual Technical Conference, June 15-18, 1998, New Orleans, Lousiana., 1998
Bengt Werner and Peter S. Magnusson, A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems, Proceedings of MASCOTS’97. , 1997
Johan Montelius and Peter S. Magnusson, Using SimICS to evaluate the Penny system, Proceedings of ILPS’97. , 1997
Peter S. Magnusson, Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter, Proceedings of Winter Simulation Conference 97. , 1997
Peter S. Magnusson and Bengt Werner, Efficient Memory Simulation in SimICS, 28th Annual Simulation Symposium, 1995. , 1995
Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hållberg, Johan Högberg, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Simics: A Full System Simulation Platform, IEEE Computer, February, 2002, 2002
Lars Albertsson and Peter S. Magnusson, Using Complete System Simulation for Temporal Debugging of General Purpose Operating Systems and Workloads, Proceedings of MASCOTS 2000., 2000
Simics User Bibliography
Simics has been used by a number of research groups over the years. Below is selection of publications where Simics was used as a tool to support the research. Typically I would not have been involved directly, but I’m proud of the benefit that Simics has provided to the academic community and thought I would bask in some of the glory.
Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura, and Wladek Olesinski.: Flexible Cache Error Protection Using an ECC FIFO. Second International Workshop on Network on Chip Architectures (held in conjunction with 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42)). 2009 Dec
Doe Hyun Yoon and Mattan Erez: Slicing Based Code Parallelization for Minimizing Inter-processor Communication. Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), Portland, OR, November 2009. 2009 Nov
Mahmut Kandemir, Yuanrui Zhang, Sai Prasanth Muralidhara, Ozcan Ozturk, and Sri Hari Krishna Narayanan: Checkpoint and Restore for SystemC Models. Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems (CASES 09). 2009 Oct
Marius Monton, Jakob Engblom, and Mark Burton: Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. Forum on Specification and Design Language (FDL 2009). 2009 Sep
Abhishek Bhattacharjee, Margaret Martonosi: NZTM: Nonblocking Zero-indirection Transactional Memory. International Conference on Parallel Architectures and Compilation Techniques (PACT-18). 2009 Sep
Fuad Tabba, Mark Moir, James Goodman, Andrew Hay and Cong Wang.: Embedded Multicore Virtual Platforms. 21st ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2009). 2009 Aug
Jakob Engblom: A HyperTransport-based cluster memory highway. Embedded Multicore: An Introduction, Freescale Manual EMBMCRM Rev 0. 2009 Jul
H. Montaner, F. Silla, and J. Duato: Memory Mapped ECC: Low-Cost Error Protection for Last Level Caches. Fifth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2009). 2009 Jul
Doe Hyun Yoon and Mattan Erez: A Case for an Interleaving Constrained Shared-Memory Multi-Processor. International Symposium on Computer Architecture (ISCA-36). 2009 Jun
Jie Yu and Satish Narayanasamy: A low-cost solution for developing reliable Linux-based space computers for on-board data handling. International Symposium on Computer Architecture (ISCA-36). 2009 Jun
Violante, M. and Esposti, M. L.: INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors. 15th IEEE International On-Line Testing Symposium (IOLTS 2009). 2009 Jun
Colin Blundell, Milo M.K. Martin, and Thomas F. Wenisch: Thread Criticality Predictors for Dynamic Power, Performance, and Resource Management in Chip Multiprocessors. International Symposium on Computer Architecture (ISCA-36). 2009 Jun
Abhishek Bhattacharjee, Margaret Martonosi: Transactional Value Prediction. International Symposium on Computer Architecture (ISCA-36). 2009 Jun
Fuad Tabba, Andrew W. Hay, and James R. Goodman: IBM System z10 firmware simulation. ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009). 2009 Feb
S. Koerner, A. Kohler, J. Babinsky, H. Pape, F. Eickhoff, S. Kriese, H. Elfering: Flexible Hardware Acceleration for Instruction-Grain Lifeguards. IBM Journal of Research and Development. 2009 Jan
Shimin Chen, Michael Kozuch, Theodoros Strigkos, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, and Evangelos Vlachos: Switch-Based Packing Technique for Improving Token Coherence Scalability. IEEE Micro, Jan/Feb 2009 Special Issue: Micro’s Top Picks in Computer Architecture Conferences. 2009 Jan
Blas Cuesta, Antonio Robles, and José Duato: Dependence-Aware Transactional Memory for Increased Concurrency. The Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2008). 2008 Dec
Hany E. Ramadan, Christopher J. Rossbach, and Emmett Witchel: TxLinux: Using and Managing Transactional Memory in an Operating System. 41st International Symposium on Microarchitecture (MICRO 41). 2008 Nov
Christopher J. Rossbach, Owen S. Hofmann, Donald E. Porter, Hany E. Ramadan, Aditya Bhandari, Emmett Witchel: Design of a reconfigurable optical interconnect for large-scale multiprocessor networks. Communications of the ACM (CACM), September 2008. 2008 Sep
Inigo Artundo, Wim Heirman, Christof Debaes, Joni Dambre, Jan Van Campenhout and Hugo Thienpont: Predictor Virtualization. SPIE Photonics Europe. 2008 Apr
Ioana Burcea, Stephen Somogyi, Andreas Moshovos and Babak Falsafi: A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 2008 Mar
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi and Ken Mai: Predicting the Performance of Recon?gurable Optical Interconnects in Distributed Shared-Memory Systems. International Symposium on Field Programmable Gate Arrays (FPGA). 2008 Feb
W. Heirman, J. Dambre, I. Artundo, C. Debaes, H. Thienpont, D. Stroobandt, J. Van Campenhout: Improving Token Coherence by Multicast Coherence Messages. Photonic Network Communications. 2008 Feb
Blas Cuesta, Antonio Robles, and José Duato: TxLinux: Using and Managing Transactional Memory in an Operating System. 16th Euromicro International Conference on Parallel, Distributed and network-based Processing (PDP 2008). 2008 Feb
Christopher J. Rossbach, Owen S. Hofmann, Donald E. Porter, Hany E. Ramadan, Aditya Bhandari, Emmett Witchel: Diffractive design of a Selective Broadcaster in Recon?gurable Optical Interconnects. 21th ACM Symposium on Operating Systems Principles (SOSP 2007),. 2007 Oct
I. Artundo, L. Desmet, C. Debaes, H. Thienpont: MARTE: UML-based Hardware Design from Modeling to Simulation. Proceedings of the 20th Annual Meeting of the IEEE LEOS. 2007 Oct
Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser: Predicting reconfigurable interconnect performance in distributed shared-memory systems. Forum on specification & Design Languages (FDL) 2007. 2007 Aug
Heirman, W.; Dambre, J.; Artundo, I.; Debaes, C.; Thienpont, H.; Stroobandt, D.; Van Campenhout, J.: Performance Evaluation of Large Reconfigurable Interconnects for Multiprocessor Systems. Integration, the VLSI Journal. Elsevier B.V. Vol. 40. July 2007. 382-393
Heirman, W.; Artundo, I.; Dambre, J.; Debaes, C.; Pham Doan, T.; Bui Viet, K.; Thienpont, H.; Van Campenhout, J.: SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. Proceedings of the International Symposium on Electrical – Electronics Engineering (ISEE 2007). July 2007. pp. 145-150.
Jianwei Chen, Michel Dubois, Per Stenström: Synthetic Traffic Generation as a Tool for Dynamic Interconnect Evaluation. IEEE Micro. July 2007.
Heirman, W.; Dambre, J.; Van Campenhout, J.: MetaTM/TxLinux: Transactional Memory For An Operating System. ACM Press. June 2007. pp. 65-72.
Hany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Aditya Bhandari, Emmett Witchel: Porting SPARTAN kernel to SPARC V9 architecture. International Symposium on Computer Architecture 2007 (ISCA 2007). June 2007.
Jakub Jermár: An Effective Starvation Avoidance Mechanism to Enhance the Token Coherence Protocol. Masters Thesis, Charles University in Prague, Faculty of Mathematics and Physics, Department of Software Engineering. April 2007.
Blas Cuesta, Antonio Robles, and José Duato: Leveraging Wire Properties at the Microarchitecture Level. The Fifteen Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2007). February 2007.
Love Kothari and Nicholas P. Carter, Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices, IEEE Transactions on Computers, February 2007 issue., 2007
Concepts and components of full-system simulation of distributed memory parallel computers. Ridruejo, F. J., Miguel-Alonso, J., and Navaridas, J. 2007. In Proceedings of the 16th international Symposium on High Performance Distributed Computing (Monterey, California, USA, June 25 – 29, 2007). HPDC ’07. ACM Press, New York, NY, 225-226. DOI= http://doi.acm.org/10.1145/1272366.1272402
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors, Sebastian Herbert and Diana Marculescu, International Symposium on Low Power Electronics and Design, Proceedings of the 2007 international symposium on Low power electronics and design, Portland, OR, USA, Pages: 38 – 43, ISBN:978-1-59593-709-4
Chang, J. and Sohi, G. S. 2007. Cooperative cache partitioning for chip multiprocessors. In Proceedings of the 21st Annual international Conference on Supercomputing (Seattle, Washington, June 17 – 21, 2007). ICS ’07. ACM Press, New York, NY, 242-252. DOI= http://doi.acm.org/10.1145/1274971.1275005
Chen, G., Li, F., and Kandemir, M. 2007. Compiler-directed application mapping for NoC based chip multiprocessors. In Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools (San Diego, California, USA, June 13 – 15, 2007). LCTES ’07. ACM Press, New York, NY, 155-157. DOI= http://doi.acm.org/10.1145/1254766.1254796
Holistic Debugging — Enabling Instruction Set Simulation for Software Quality Assurance, Lars Albertsson, MASCOTS, pp. 96-103, 14th IEEE International Symposium on Modeling, Analysis, and Simulation, 2006
Alameldeen A.R., Wood, D.A, IPC Considered Harmful for Multiprocessor Workloads, Micro, IEEE, Volume 26, Issue 4, Page(s): 8-17, July – August 2006., 2006
Andrés Ortiz, Julio Ortega, Antonio F. Díaz, Alberto Prieto, Protocol Offload Evaluation Using Simics, International Conference on Cluster Computing 2006, September 2006., 2006
Artundo I, Desmet L, Heirman W, Debaes C, Dambre J, Van Campenhout J.M., Thienpont H, Selective optical broadcast component for reconfigurable multiprocessor interconnects, IEEE Journal on Selected Topics in Quantum Electronics: Special Issue on Optical Communication. IEEE LEOS. Vol. 12 (4). 2006. pp. 828-837, July – August 2006., 2006
Artundo, I; Desmet, L; Heirman, W; Debaes, C; Dambre, J; Van Campenhout, J; Thienpont, H, Selective optical broadcasting in reconfigurable multiprocessor interconnects, Proc. of SPIE Photonics Europe. Vol. 6185. 2006. (61850J), April 2006., 2006
Dan Wallin, Henrik Löf, Erik Hagersten and Sverker Holmgren, Multigrid and GaussSeidel Smoothers Revisited: Parallelization on Chip Multiprocessors, International Conference on Supercomputing (ICS), July 2006., 2006
Feihui Li, Chrysostomos Nicopoulos, Thomas Richardson, Yuan Xie, Vijaykrishnan Narayanan, and Mahmut Kandemir: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, International Symposium on Computer Architecture (ISCA), June 2006. , 2006
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors, , 2006
G. Chen, M. Kandemir, and F. Li: Software techniques for efficient SoC design: Energy-aware computation duplication for improving reliability in embedded chip multiprocessors, 2006 Conference on Asia South Pacific Design Automation (ASP-DAC 2006), June 2006 , 2006
Guangyu Chen, Feihui Li, Mahmut Kandemir, Mary Jane Irwin, Reducing NoC Energy Consumption Through Compiler-Directed Channel Voltage Scaling, Programming Language Design and Implementation (PLDI), June 2006. , 2006
Hill, Ben Liblit, Michael M. Swift and David A. Wood, Supporting Nested Transactional Memory in LogTM, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006., 2006
International Symposium on Computer Architecture (ISCA), June 2006. , 2006
Jakob Engblom, Bengt Werner, and Guillaume Girard: Testing Embedded Software using Simulated Hardware, Proc. Embedded Real-Time Software (ERTS 2006), Toulouse, France, January 2006. , 2006
Jakob Engblom, C.W. Mattias Holm, A Fully Virtual Multi-Node 1553 Bus Computer System, Data Systems in Aerospace (DASIA), May 2006., 2006
Jakob Engblom, Debugging Real-Time Multiprocessor Systems, Class and Paper presented at the Embedded Systems Conference Silicon Valley (ESC), San Jose, USA, April 2006., 2006
Jichuan Chang and Gurindar S. Sohi: Cooperative Caching for Chip Multiprocessors, International Symposium on Computer Architecture (ISCA), June 2006. , 2006
Karin Strauss, Xiaowei Shen, and Josep Torrellas: , 2006
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill and David A. Wood, LogTM: Log-based Transactional Memory, International Symposium on High Performance Computer Architecture (HPCA), February 2006., 2006
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John B. Carter: Interconnect-Aware Coherence Protocols for Chip Multiprocessors, International Symposium on Computer Architecture (ISCA), June 2006. , 2006
Luis Ceze, James Tuck, Josep Torrellas, and Calin Cascaval: Bulk Disambiguation of Speculative Threads in Multiprocessors, International Symposium on Computer Architecture (ISCA), June 2006. , 2006
Mahmut Taylan Kandemir: Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 11, Issue 2, April 2006. , 2006
Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. , 2006
Mikael Bergqvist, Jakob Engblom, Mikael Patel, Lars Lundegård, Some Experience From the Development of a Simulator for a Telecom Cluster (CPPemu), IASTED International Conference on Software Engineering and Applications, November 2006., 2006
Min Xu, Rastislav Bodik and Mark D. Hill, A Regulated Transitive Reduction (RTR) for Longer Memory Race Recording, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006., 2006
Nauman Rafique, Won-Taek Lim, and Mithuna Thottethodi, Architectural Support for Operating System-Driven CMP Cache Management, Parallel Architectures and Compilation Techniques (PACT), September 2006., 2006
Saisanthosh Balakrishnana and Gurindar S. Sohi: Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs, International Symposium on Computer Architecture (ISCA), June 2006. , 2006
Stavros Harizopoulos and Anastassia Ailamaki, Improving Instruction Cache Performance in OLTP, ACM Transactions on Database Systems (TODS), September 2006., 2006
Stephen Somogyi, Thomas Wenisch, Anastassia Ailamaki, Babak Falsafi, and Andreas Moshovos, Spatial Memory Streaming, International Symposium on Computer Architecture (ISCA), June 2006., 2006
Wenisch T.F., Wunderlich R.E., Ferdman M., Ailamaki A., Falsafi B., Hoe J.C., SimFlex: Statistical Sampling of Computer System Simulation, Micro, IEEE, Volume 26, Issue 4, Page(s): 18-31, July – August 2006., 2006
Albert Meixner, Daniel J. Sorin, Dynamic Verification of Sequential Consistency, 32nd Annual International Symposium on Computer Architecture (ISCA), June 2005., 2005
Alexandra Fedorova, Margo Seltzer, Christopher Small and Daniel Nussbaum, Performance Of Multithreaded Chip Multiprocessors And Implications For Operating System Design, to appear in Proceedings of USENIX 2005 Annual Technical Conference Anaheim, CA, April 2005., 2005
F.J. Ridruejo, A. Gonzalez, J. Miguel-Alonso, TrGen: a Traffic Generation System for Interconnection Network Simulators, Proceedings of the 7th Workshop on High Performance Scientific and Engineering Computing (HPSEC’05), Oslo, Norway, June 2005., 2005
Jakob Engblom, David Kågedal, Andreas Moestedt, and Johan Runeson, Developing Embedded Networked Products using the Simics Full-System Simulator,Proc. 16th IEEE International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC 2005), Berlin, Germany, September 2005., 2005
John D. Davis, Cong Fu, and James Laudon: The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors, ACM SIGARCH Computer Architecture News, Volume 33 Issue 4, November 2005., 2005
Jonas Myhrman, Pierre Svärd, Studying Fault Injection in WCDMA Base Station Processors Using Simics Simulator, Master’s Thesis Computer Science and Engineering Program, Chalmers University of Technology, Göteborg, June, 2005., 2005
Mathias Thore, Automatic detection of race conditions in OSE using vector clocks, Master’s Thesis Information Technology, Uppsala University, Uppsala, June, 2005., 2005
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M.K. Martin and David A. Wood, Improving Multiple-CMP Systems Using Token Coherence, International Symposium on High Performance Computer Architecture (HPCA), February 2005., 2005
Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood, Multifacet’s General Execution-driven Multiprocessor Simulator (GEMS) Toolset, Computer Architecture News (CAN), September 2005., 2005
Min Xu, Rastislav Bodik and Mark D. Hill, A Serializability Violation Detector for Shared-Memory Server Programs, Programming Language Design and Implementation (PLDI), June 2005., 2005
Nikrouz Faroughi, Profiling of Parallel Processing Programs on Shared Memory Multiprocessors Using Simics, Workshop on Binary Instrumentation and Applications, held in conjunction with the 14th International Conference on Parallel Architectures and Compilation Techniques PACT-14, St. Louis, MO, September, 2005., 2005
Thomas Wenisch, Stephen Somogyi, Nikos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, and Babak Falsafi, Temporal Streaming of Shared Memory, ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2005, 2005
W. Heirman, J. Dambre, J. Van Campenhout, Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems, Proceedings of the 19th IEEE International Parallel & Distributed Processing Symposium, Denver, Colorado, April, 2005., 2005
Wallin D., Zeffer H., Karlsson M., Hagersten E., Vasa: A Simulator Infrastructure with Adjustable Fidelity, In the 17th IASTED International Conference on PARALLEL AND DISTRIBUTED COMPUTING AND SYSTEMS (PDCS 2005), Phoenix, Arizona, USA; November 2005, 2005
Zeshan Chishti, Michael D. Powell, and T. N. Vijaykumar, Optimizing Replication, Communication, and Capacity Allocation in CMPs, ISCA 2005., 2005
Alaa R. Alameldeen and David A. Wood, Adaptive Cache Compression for High-Performance Processors , International Symposium on Computer Architecture (ISCA-31), June 2004., 2004
Alexandra Fedorova, Christopher Small, Daniel Nussbaum, and Margo Seltzer, Chip Multithreading Systems Need a New Operating System Scheduler , 11th ACM SIGOPS European Workshop, September 2004., 2004
Bertrand Bastien, A Technique for Performing Fault Injection in System Level Simulations for Dependability Assessment, Master’s Thesis, University of Virginia, January 2004, 2004
C. Liu, A. Sivasubramaniam, M. Kandemir, Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values, Euromicro Conference on Parallel and Distributed Processing (PDP 2004), February 2004, 2004
C. Liu, A. Sivasubramaniam, M. Kandemir, Organizing the Last Line of Defense before hitting the Memory Wall for CMPs, International Symposium on High Performance Computer Architecture (HPCA 2004), February 2004, 2004
Dan Wallin and Erik Hagersten, Bundling: Reducing the Overhead of Multiprocessor Prefetchers , International Parallel and Distributed Processing Symposium (IPDPS), April 2004, 2004
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood, Using Speculation to Simplify Multiprocessor Design, International Parallel and Distributed Processing Symposium (IPDPS), April 2004, 2004
Daniel Nussbaum, Alexandra Fedorova and Christopher Small, An overview of the Sam CMT simulator kit , Technical Report TR-2004-133, Sun Microsystems Research Labs, March 2004, 2004
E. Lattanzi, A. Gayasen, M. Kandemir, V. Narayanan, L. Benini, A. Bogliolo, Improving Java Performance by Dynamic Method Migration on FPGAs. Proceedings of the 11th Reconfigurable Architectures Workshop (RAW 2004), April 2004. (Abstract and PDF) , 2004
Erik Berg and Erik Hagersten, StatCache: A Probabilistic Approach to Efficient and Accurate Data Locality Analysis , International Parallel and Distributed Processing Symposium (ISPASS-2004), March 2004, 2004
Francisco J. Villa, , Manuel E. Acacio, and José M. García, On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs , 4th International Conference on Computing Sciences (ICCS 2004), June 2004., 2004
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk, Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth , 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), October 2004., 2004
Jialin Dou and Marcelo Cintra, Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization , International Conference on Parallel Architecture and Compilation Techniques (PACT 2004), September-October 2004., 2004
Magnus Ekman and Per Stenström, A Case for Multi-Level Main Memory , 3rd Workshop on Memory Performance Issues (WMPI-2004), June 2004., 2004
Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk, SIMFLEX: A Fast, Accurate, Flexible Full System Simulation Framework for Performance Evaluation of Server Architecture , SIGMETRICS Performance Evaluation Review, Vol. 31, No. 4, pp. 31-35, April 2004., 2004
Simon Kågström, Lars Lundberg, and Håkan Grahn, A novel method for adding multiprocessor support to a large and complex uniprocessor kernel, International Parallel and Distributed Processing Symposium (IPDP), April 2004, 2004
Stephen Somogyi, Thomas F. Wenisch, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, and Babak Falsafi, Memory Coherence Activity Prediction in Commercial Workloads , 3rd Workshop on Memory Performance Issues (WMPI-2004), June 2004., 2004
Tulika Mitra, Abhik Roychoudhury, and Qinghua Shen, Impact of Java Memory Model on Out-of-Order Multiprocessors , International Conference on Parallel Architecture and Compilation Techniques (PACT 2004), September-October 2004., 2004
Yue Luo and Lizy Kurian John, Locality-Based Online Trace Compression, , IEEE Transactions on Computers, volume 53, issue 6, June 2004. , 2004
Alaa R. Alameldeen and David A. Wood, Addressing Workload Variability in Architectural Simulations, IEEE Micro Special Issue on Top Picks in Computer Architecture, November-December 2003, 2003
Alaa R. Alameldeen and David A. Wood, Variability in Architectural Simulations of Multi-threaded Workloads, 9th International Symposium on High Performance Computer Architecture (HPCA-9), February 2003, 2003
Alaa R. Alameldeen, Milo M.K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill and David A. Wood, Simulating a $2M Commercial Server on a $2K PC, IEEE Computer, February 2003., 2003
Bradford M. Beckmann and David A. Wood, TLC: Transmission Line Caches, 36th International Symposium on Microarchitecture (MICRO), December 2003, 2003
Dan Wallin and Erik Hagersten, Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors, 6th IEEE International Parallel and Distributed Processing Symposium , April 2003., 2003
Dan Wallin, Henrik Johansson, and Sverker Holmgren, Cache Memory Behavior of Advanced PDE Solvers, Parallel Computing 2003 (ParCo2003), August 2003., 2003
Daniel J. Sorin, Mark D. Hill, and David A. Wood, Dynamic Verification of End-to-End Multiprocessor Invariants, International Conference on Dependable Systems and Networks (DSN 2003), June 2003., 2003
Dinesh C Suresh, Satya R. Mohanty, Walid A. Najjar, Laxmi N. Bhuyan, and Frank Vahid, Loop Level Analysis of Security and Network Applications, Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-03) held in Conjunction with HPCA-9, February 2003., 2003
Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, and Greg Stitt, Profiling Tools for Hardware/Software Partitioning of Embedded Applications, The 2003 ACM SIGPLAN Conf. on Languages, Compilers and Tools for Embedded Systems (LCTES 2003), June 2003.
Fangyong Hou, Zhiying Wang, Zhen Liu, and Yun Liu, Avoid Powerful Tampering by Malicious Host, Grid and Cooperative Computing: Second International Workshop (GCC 2003), December 7-10, 2003.
Fredrik Warg and Per Stenström, Improving Speculative Thread-Level Parallelism through Module Run-Length Prediction, 6th IEEE International Parallel and Distributed Processing Symposium, April 2003.
Jianwei Chen, Michel Dubois, and P. Stenström, SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2003), March 2003.
Jim Nilsson, Anders Landin, and Per Stenström, Coherence Predictor Cache: A Resource Efficient Coherence Message Prediction Infrastructure, 6th IEEE International Parallel and Distributed Processing Symposium, April 2003.
Martin Karlsson, Kevin E. Moore, Erik Hagersten, and David A.Wood, Memory System Behavior of Java-Based Middleware, Appears in the proceedings of the 9th Annual International Symposium on High-Performance Computer Architecture (HPCA-9) Anaheim, CA, February 8-12, 2003.
Milo M. K. Martin, Mark D. Hill, and David A. Wood, Token Coherence: Decoupling Performance and Correctness, International Symposium on Computer Architecture (ISCA-30), June 2003.
Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood, Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared Memory Multiprocessors, International Symposium on Computer Architecture (ISCA-30), June 2003.
Milo M.K. Martin, Mark D. Hill and David A. Wood, Token Coherence: A New Framework for Shared-Memory Multiprocessors, IEEE Micro Special Issue on Top Picks in Computer Architecture, November-December 2003.
Min Xu, Rastislav Bodik, and Mark D. Hill, A “Flight Data Recorder” for Enabling Full system Multiprocessor Deterministic Replay, International Symposium on Computer Architecture (ISCA-30), June 2003.
Peter Rundberg and Per Stenström, Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections, 6th IEEE International Parallel and Distributed Processing Symposium, April 2003.
Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin, Mark D. Hill and David A. Wood, Evaluating Non-deterministic Multi-threaded Commercial Workloads, appears in the proceedings of the Computer Architecture Evaluation using Commercial Workloads (CAECW-02), February 2, 2002.
Carl J. Mauer, Mark D. Hill and David A. Wood, Full System Timing-First Simulation, appears in the proceedings of the 2002 ACM Sigmetrics Conference on Measurement and Modeling of Computer Systems June, 2002.
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood, SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery, appears in the proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002.
Daniel J. Sorin, Using Lightweight Checkpoint/Recovery to Improve the Availability and Designability of Shared Memory Multiprocessors, PhD Thesis, University of Wisconsin-Madison, August 2002.
Jianwei Chen, Michel Dubois, Per Stenström, Integrating Complete-System and User-level Performance/ Power Simulators: The SimWattch Approach Technical Report 02-20. Department of Computer Engineering, Chalmers University of Technology., 2002
Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood, Memory Characterization of the ECperf Benchmark 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with the 29th International Symposium on Computer Architecture (ISCA-29), May 2002.
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood, Bandwidth Adaptive Snooping, appears in the proceedings of the 8th Annual International Symposium on High-Performance Computer Architecture (HPCA-8), Cambridge, MA, February 2-6, 2002.
Morris Marden, Shih-Lien Lu, Konrad Lai, Mikko Lipasti, Comparison of Memory System Behavior in Java and Non-Java Commercial Workloads, appears in the proceedings of the Computer Architecture Evaluation using Commercial Workloads (CAECW-02), February 2, 2002.
Ryan Rakvic, Ed Grochowski, Bryan Black, Murali Annavaram, Trung Diep, John P. Shen (Intel Corporation), Performance Advantage of the Register Stack in Intel Itanium Processors , 2nd Workshop on Explicitly Parallel Instruction Computing Architecture and Compilers, November 2002.
Lars Albertsson, Simulation-Based Debugging of Soft Real-Time Applications, Proceedings of the Real-Time Application Symposium (RTAS 2001), May 2001.
Jim Nilsson and Fredrik Dahlgren, Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors, Published in Proceedings of the 2000 International Parallel and Distributed Processing Symposium, Cancun, Mexico, May 2000.
Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood, Timestamp Snooping: An Approach for Extending SMPs, Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), November 2000.
Todd Bezenek, Trey Cain, Ross Dickson, Tim Heil, Milo Martin, Collin Mccurdy, Ravi Rajwar, Eric Weglarz, Craig Zilles, and Mikko Lipasti, Characterizing a Java Implementation of TPC-W, Presentation at the 3rd Workshop On Computer Architecture Evaluation Using Commercial Workloads (CAECW), January 2000.
Jim Nilsson and Fredrik Dahlgren, Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors, in Proceedings of the 1999 International Conference on Parallel Processing, September 1999.